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P521-23
Low Phase Noise PECL VCXO (100MHz to 200MHz)
FEATURES
* * * * * * * * * 100MHz to 200MHz Fundamental Mode Crystal. Output range: 100MHz - 200MHz. Complementary PECL outputs. Selectable OE Logic (enable high or enable low). Integrated variable capacitors. High pull linearity: < 5%. +/- 125 ppm pull range Supports 2.5V or 3.3V-Power Supply. Available in 16-pinTSSOP.
PIN CONFIGURATION
OSCOFFSEL GNDOSC VCON XIN XOUT
OECTRL
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDDOSC BUFZSEL OESEL VDDANA VDDBUF QBAR Q GND
P521-23
DNC GND
DESCRIPTIONS
P521-23 is a VCXO IC specifically designed to pull high frequency fundamental crystals. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. The chip provides a low phase noise, low jitter PECL differential clock output.
OUTPUT ENABLE LOGIC SELECTION
OESEL (Pad #14) 0 (Default) 1 OECTRL (Pad #22) 0 (Default) 1 0 1 (Default) State Output enabled Tri-state Tri-state Output enabled
BLOCK DIAGRAM
Pad #14, 22: Bond to GND to set to "0", bond to VDD to set to "1" No connection results to "default" setting through internal pull-up/-down. Pad #22: Logical states defined by PECL VIH and VIL levels.
OE VCON Oscillator X+ XQ Q
Amplifier w/ integrated varicaps
HIGH IMPEDANCE BUFFER LOGIC SELECTION
BUFZSEL (Pad #15) 0 (Default) State Hi Z if Output is Disabled (Q=0) and (Qbar=1) if Output Disabled
P521-23
1
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 [www.phaselink.com]
Rev 7/28/04 Page 1
P521-23
Low Phase Noise PECL VCXO (100MHz to 200MHz)
PAD ASSIGNMENT AND DESCRIPTION
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Name
OSCOFFSEL GNDOSC VCON XIN XOUT OECTRL DNC GND GND Q QBAR VDDBUF VDDANA OESEL BUFZSEL VDDOSC
Description
Oscillator Off Selection input pad. When low, turns off the oscillator when output is disabled. When high (default), oscillator running when output is disabled. Internal pull-up GND connection for oscillator circuitry. Control Voltage input. Use this pin to change the output frequency by varying the applied Control Voltage. Crystal oscillator input pin. Crystal oscillator output pin. OE input pad. See table on page 1. Do Not Connect. Ground connection. Ground connection. PECL Output. PECL complementary output. VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. VDD connection for analog circuitry. VDDANA should be separately decoupled from other VDDs whenever possible. Selector input to choose the OE control logic. See table on page 1. Output impedance selector VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other VDDs whenever possible.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 [www.phaselink.com]
Rev 7/28/04 Page 2
P521-23
Low Phase Noise PECL VCXO (100MHz to 200MHz)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection
SYMBOL
VDD VI VO TS TA TJ
MIN.
VSS-0.5 VSS-0.5 -65 0
MAX.
4.6 VDD+0.5 VDD+0.5 150 70 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
2. Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Crystal Pullability Recommended ESR
SYMBOL
FXIN CL (xtal) C0 C0/C1 (xtal) RE
CONDITIONS
Parallel Fundamental Mode VCON = 1.65V AT cut AT cut
MIN.
100
TYP.
MAX.
200
UNITS
MHz pF
5.0 3.5 250 30
pF
3. Voltage Control Crystal Oscillator PARAMETERS
VCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW 0V VCON 3.3V, -3dB 2000 25 70
SYMBOL
TVCXOSTB
CONDITIONS
From power valid XTAL C0/C1 < 250 VCON = 1.65V 1.65V at room temperature VCON = 0 to 3.3V
MIN.
250*
TYP.
MAX.
10
UNITS
ms ppm
125* 3.3 - 8.8* 5*
ppm pF % ppm/V k kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 [www.phaselink.com]
Rev 7/28/04 Page 3
P521-23
Low Phase Noise PECL VCXO (100MHz to 200MHz)
4. General Electrical Specifications PARAMETERS
Supply Current (Loaded Outputs) Output valid after OE enabled Operating Voltage Output Clock Duty Cycle Short Circuit Current VDD @ Vdd - 1.3V (PECL)
SYMBOL
IDD
CONDITIONS
at 3.3V @ 155MHz Oscillator off Oscillator on
MIN.
TYP.
MAX.
55 10 50
UNITS
mA ms ns V % mA
2.25 45 50 50
3.63 55
5. Jitter specifications PARAMETERS
Period jitter RMS at 155MHz Period jitter peak-to-peak at 155MHz Accumulated jitter RMS at 155MHz Accumulated jitter peak-to-peak at 155MHz Random Jitter Integrated jitter RMS at 155MHz
Measured on Wavecrest SIA 3000
CONDITIONS
At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. "RJ" measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5 18.5 2.5 24 2.5 0.25
MAX.
20
UNITS
ps
27
ps ps
0.35
ps
6. Phase noise specifications PARAMETERS
Phase Noise relative to carrier
FREQUENCY
155.52MHz
10Hz
-75
100Hz
-100
1kHz
-125
10kHz
-140
100kHz
-145
1MHz
-150
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 [www.phaselink.com]
Rev 7/28/04 Page 4
P521-23
Low Phase Noise PECL VCXO (100MHz to 200MHz)
7. PECL Electrical Characteristics PARAMETERS Output High Voltage Output Low Voltage SYMBOL V OH V OL CONDITIONS R L = 50 to (V DD - 2V) (see figure) MIN. V DD - 1.025 V DD - 1.620 MAX. UNITS V V
8. PECL Switching Characteristics PARAMETERS Clock Rise Time Clock Fall Time
PECL Levels Test Circuit
OUT VDD OUT
SYMBOL
tr tf
CONDITIONS @20/80% - PECL @80/20% - PECL
MIN.
TYP. 0.6 0.5
MAX. 1.5 1.5
UNITS ns ns
PECL Output Skew
50
2.0V 50%
50 OUT OUT tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT 80% 50% 20% OUT tR tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 [www.phaselink.com]
Rev 7/28/04 Page 5
P521-23
Low Phase Noise PECL VCXO (100MHz to 200MHz)
PACKAGE INFORMATION
16 PIN Narrow SOIC, TSSOP ( mm )
SOIC Symbol A A1 B C D E H L e Min. 1.35 0.10 0.33 0.19 9.80 3.80 5.80 0.40 1.27 BSC Max. 1.75 0.25 0.51 0.25 10.00 4.00 6.20 1.27 0.45 Min. 0.05 0.19 0.09 4.90 4.30 TSSOP Max. 1.20 0.15 0.30 0.20 5.10 4.50 6.40 BSC 0.75 0.65 BSC A1 B C L e A D E H
ORDERING INFORMATION
PART NUMBER
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
P521-23
PART NUMBER
DC
TEMPERATURE
C=COMMERCIAL
PACKAGE TYPE
D=Die O=TSSOP
Order Number P521-23DC P521-23OC-R P521-23OC
Marking P521-23DC P521-23 OC P521-23 OC
Package Option Die - Waffle Pack TSSOP - Tape and Reel TSSOP - Tube
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 [www.phaselink.com] Rev 7/28/04 Page 6

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